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ST16C650AIQ48 データシート(PDF) 3 Page - Exar Corporation |
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ST16C650AIQ48 データシート(HTML) 3 Page - Exar Corporation |
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3 / 52 page  ST16C650A 3 REV. 5.0.2 2.90V TO 5.5V UART WITH 32-BYTE FIFO PIN DESCRIPTIONS NAME 44- PLCC PIN # 48- TQFP PIN # TYPE DESCRIPTION 16 (Intel) MODE DATA BUS INTERFACE. The SEL pin is connected to VCC. A2 A1 A0 29 30 31 26 27 28 I Address bus lines [2:0] A2:A0 selects internal UART’s configuration registers. D7 D6 D5 D4 D3 D2 D1 D0 9 8 7 6 5 4 3 2 4 3 2 47 46 45 44 43 IO Data bus lines [7:0] (bidirectional) IOR# 24 19 I Input/Output Read (active low) The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], places it on the data bus to allow the host processor to read it on the leading edge. Its function is the same as IOR, except it is active low. Either an active IOR# or IOR is required to transfer data from 650A to CPU during a read operation. If this input is unused, it should be connected to VCC to minimize supply current. IOR 25 20 I Input/Output Read (active high) Same as IOR# but active high. If this input is unused, it should be connected to GND to minimize supply current. IOW# 20 16 I Input/Output Write (active low) The falling edge instigates the internal write cycle and the trailing edge transfers the data byte on the data bus to an internal register pointed by the address lines [A2:A0]. Its function is the same as IOW, except it is active low. Either an active IOW# or IOW is required to transfer data from 650A to the Intel type CPU during a write operation. If this input is unused, it should be connected to VCC to minimize supply current. IOW 21 17 I Input/Output Write (active high) Same as IOW# but active high. If this input is unused, it should be connected to GND to minimize supply current. CS0 14 9 I Chip Select 0 input (active high) This input selects the ST16C650A device. If CS1 or CS2# is used as the chip select then this pin must be connected to VCC. The 650A is selected when all three chip selects are active. See Figure 3 and Figure 4. CS1 15 10 I Chip Select 1 input (active high) This input selects the ST16C650A device. If CS0 or CS2# is used as the chip select then this pin must be connected to VCC. The 650A is selected when all three chip selects are active. See Figure 3 and Figure 4. CS2# 16 11 I Chip Select 2 input (active low) This input selects the ST16C650A device. If CS0 or CS1 is used as the chip select then this pin must be connected to GND. The 650A is selected when all three chip selects are active. See Figure 3 and Figure 4. |
同様の部品番号 - ST16C650AIQ48 |
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同様の説明 - ST16C650AIQ48 |
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