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AD5542AACPZ データシート(PDF) 5 Page - Analog Devices

部品番号 AD5542AACPZ
部品情報  2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-/12-Bit nanoDACs in LFCSP
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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AD5542AACPZ データシート(HTML) 5 Page - Analog Devices

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Preliminary Technical Data
AD5541A/AD5542A/AD5512AA
Rev. P
rA | Page 5 of 24
Parameter
Min
Typ
Max
Unit
Test Condition
POWER REQUIREMENTS
VDD
2.7
5.5
V
IDD
200
TBD
µA
VLOGIC
1.8
5.5
V
ILOGIC
200
TBD
µA
Power Dissipation
1.5
TBD
mW
1 Reference input resistance is code-dependent, minimum at 0x8555.
2 Guaranteed by design, not subject to production test.
TIMING CHARACTERISTICS
VLOGIC = 1.8 V to 5.5 V V, VDD = 5V, VREF = 2.5 V, VINH = 90% of VLOGIC, VINL = 10% of VLOGIC, AGND = DGND = 0 V; −40°C < TA < +105°C,
unless otherwise noted.
Table 2.
Parameter1, 2
Limit
Unit
Description
fSCLK
50
MHz max
SCLK cycle frequency
t1
20
ns min
SCLK cycle time
t2
10
ns min
SCLK high time
t3
10
ns min
SCLK low time
t4
5
ns min
CS low to SCLK high setup
t5
7
ns min
CS high to SCLK high setup
t6
15
ns min
SCLK high to CS low hold time
t7
10
ns min
SCLK high to CS high hold time
t8
7
ns min
Data setup time
t9
5
ns min
Data hold time (VINH = 90% of VDD, VINL = 10% of VDD)
t9
5
ns min
Data hold time (VINH = 3V, VINL = 0 V)
t10
15
ns min
LDAC pulsewidth
t11
15
ns min
CS high to LDAC low setup
t12
15
ns min
CS high time between active periods
t13
15
ns min
CLR pulsewidth
1 Guaranteed by design and characterization. Not production tested
2 All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VINL + VINH)/2.
Figure 5. Timing Diagram


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