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PD064VT2_V1.9 データシート(PDF) 8 Page - AZ Displays |
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PD064VT2_V1.9 データシート(HTML) 8 Page - AZ Displays |
8 / 22 page PD064VT2 The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page:8 Note 7-1 : In order to satisfy the quality of B/L , no matter use what kind of inverter , the output lamp current must between Min. and Max. to avoid the abnormal display image caused by B/L. Note 7-2 : The waveform of lamp driving voltage should be as closed to a perfect sine wave as possible. Note 7-3 : This value is not output voltage of inverter. The voltage of inverter must larger than the starting voltage. The Kick-off times≧1sec 7-2) Power Consumption Parameters Symbol Typ. Max. Unit Remark +3.3V Current Dissipation ICC 170 200 mA Input Signals Current (High) IIH 100 μ A VIH =+3.3V Input Signals Current (Low) IIL 100 μ A VIL =0V LCD Panel Power Consumption 0.56 0.66 W Note 7-4 Backlight Power Consumption 1.95 2.10 W Note 7-5 Note 7-4 : The power consumption of backlight is not included. Note 7-5 : Backlight lamp power consumption is calculated by IL×VL. 7-3) Input / Output signal timing chart Parameters Symbol Min. Typ. Max. Unit Note Frequency Fc=1/Tc 25.175 MHz Note 7-6 Clock High Time Tckh 10 ns Low Time Tckl 10 ns Periodic = Line Thp 31.778 μ s Note 7-6 Hsync 800 1024 clock Note 7-6 Pulse Width Thpw 2 96 200 clock Back Porch Thbp 2 49 64 clock 515 525 1024 line Note 7-6 Vsync Pulse Width Tvpw 1 2 line Back Porch Tvbp 1 33 64 line Data Setup Time Tds 10 ns Hold Time Tdh 10 ns Periodic = Line Tep 800 1024 clock Pulse Width (H) Tepw 2 640 800 clock Horizontal Display Periodic Thd 640 640 640 clock Hsync-CLK Phase Difference Thc 10 Tc-10 ns Vsync-Hsync Phase Difference Tvh 1 Thp-1 clock Note 7-6 : Tc is the period of sampling clock. In case of low-frequency, the image-flicker may occur. |
同様の部品番号 - PD064VT2_V1.9 |
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同様の説明 - PD064VT2_V1.9 |
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