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データシートサーチシステム |
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データシートサーチシステム |
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SL15316ZI-XXX データシート(PDF) 9 Page - SpectraLinear Inc |
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SL15316ZI-XXX データシート(HTML) 9 Page - SpectraLinear Inc |
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9 / 12 page  Rev 1.0, August 7, 2008 Page 9 of 12 SL15316 CL=15pF, 20 to 80% of VDD Output Rise/Fall Time tr/f6 Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD - 0.65 - ns Output Rise/Fall Time tr/f7 Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD - 0.50 - ns Cycle-to-Cycle Jitter CCJ1 FIN=25MHz Clock, all 5 clocks are at 66MHz, +/-1.0% Spread. CL=10pF, VDD=VDDO1/2=3.3V - TBD TBD ps Cycle-to-Cycle Jitter CCJ2 FIN=25MHz Clock, all 5 clocks are at 166MHz, +/-1.0% Spread. CL=10pF, VDD=VDDO1/2=3.3V - TBD TBD ps Power-down Time tPD Time from PD# falling edge to Hi-Z at outputs (Asynchronous) - 150 350 ns Power-up Time (Crystal or Clock) tPU Time from PD# rising edge to valid frequency at outputs (Asynchronous) - 3.5 5.0 ms Output Enable Time tOE Time from OE falling edge to Hi-Z at outputs (Asynchronous) - 180 450 ns Output Disable Time tOD Time from OE falling edge to Hi-Z at outputs (Asynchronous) - 180 450 ns Spread Percent Range SPR-1 Center Spread, all programmed SSCLKs +/-0.125 - +/-2.5 % Spread Percent Range SPR-2 Down Spread, all programmed SSCLKs -5.0 - -0.25 % Spread Percent Variation ΔSS% Variation of programmed Spread % -20 - 20 % Modulation Frequency FMOD Programmable, 31.5 kHz standard 25 31.5 120 kHz Power Supply Ramp Time tPSR Time for VDD reaching minimum specified value and monolithic power supply ramp - - 12 ms |
同様の部品番号 - SL15316ZI-XXX |
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同様の説明 - SL15316ZI-XXX |
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