ST8008

V0.3

8/21

2004/04/05

FUNCTIONAL DESCRIPTION

Pin Functions

SYMBOL

FUNCTION

VDD

Logic system power supply pin, connected to +2.5 to +5.5 V.

VSS

Ground pin, connected to 0 V.

V0 V2 V3

This is a multi-level power supply for the liquid crystal drive. The voltage Supply applied is

determined by the liquid crystal cell, and is changed through the use of a resistive voltage divided or

through changing the impedance using an op. amp. Voltage levels are determined based on VSS,

and must maintain the relative magnitudes shown below.

V0

V2

V3

Vss

≧

≧

≧

DI3-DI0

Input pins for display data

In 4-bit parallel input mode, input data into the 4 pins, DI3-DI0.

In serial input mode, input data into the 1 pin DI0.

Connect DI3-DI1 to VSS or VDD

Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT

PINS" in Functional Operations.

XCK

Clock input pin for taking display data

* Data is read at the falling edge of the clock pulse.

LP

Latch pulse input pin for display data

Data is latched at the falling edge of the clock pulse.

XDISPOFF

Control input pin for output of non-select level

The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the

LCD drive circuit.

When set to VSS level "L", the LCD drive output pins (SEG0~SEG79) are set to level Vss.

When set to "L", the contents of the line latch are reset, but the display data are read in the

data latch regardless of the condition of /DISPOFF. When the XDISPOFF function is canceled,

the driver outputs non-select level (V2 or V3), then outputs the contents of the data latch at the

next falling edge of the LP. At that time, if XDISPOFF removal time does not correspond to what is

shown in AC characteristics, it cannot output the reading data correctly.

Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.

FR

AC signal input pin for LCD drive waveform

The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the

LCD drive circuit.

Normally it inputs a frame inversion signal.

The LCD drive output pins' output voltage levels can be set using the line latch output signal and

the FR signal.

Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.

P/S

Interface Mode selection pin

When P/S is “H” then parallel data input mode.