LPC1343 datasheet(19/53 Pages) NXP

部品番号	LPC1343

部品情報	32-bit ARM Cortex-M3 microcontroller; up to 32 kB flash and 8 kB SRAM; USB device

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メーカー	NXP [NXP Semiconductors]

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19 / 53 page

LPC1311_13_42_43_1

Product data sheet

Rev. 01 — 11 December 2009

19 of 53

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

7.10.1 Features

• 16-byte receive and transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Fractional divider for baud rate control, auto baud capabilities and FIFO control

mechanism that enables software ﬂow control implementation.

• Support for RS-485/9-bit mode.

• Support for modem control.

7.11 SSP serial I/O controller

The LPC1311/13/42/43 contain one SSP controller. The SSP controller is capable of

operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and

slaves on the bus. Only a single master and a single slave can communicate on the bus

during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits

to 16 bits of data ﬂowing from the master to the slave and from the slave to the master. In

practice, often only one of these data ﬂows carries meaningful data.

7.11.1 Features

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

7.12 I2C-bus serial I/O controller

The LPC1311/13/42/43 contain one I2C-bus controller.

The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line

(SCL) and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be

controlled by more than one bus master connected to it.

7.12.1 Features

• The I2C-bus interface is a standard I2C-bus compliant interface with open-drain pins.

The I2C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.

• Easy to conﬁgure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

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