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TS32MCF80 データシート(PDF) 9 Page - Transcend Information. Inc.

部品番号 TS32MCF80
部品情報  80X CompactFlash Card
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メーカー  TRANSCEND [Transcend Information. Inc.]
ホームページ  http://www.transcendusa.com
Logo TRANSCEND - Transcend Information. Inc.

TS32MCF80 データシート(HTML) 9 Page - Transcend Information. Inc.

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S3
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32
2
2M
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M~
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1G
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C
CF
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F8
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80X CompactFlash Card
Transcend Information Inc.
V1.1
9
D15 - D00
(PC Card Memory Mode)
D15 - D00
(PC Card I/O Mode)
D15 - D00
(True IDE Mode)
I/O
31,30,29,28,
27,49,48,47,
6,5,4,3,2,
23, 22, 21
These lines carry the Data, Commands and Status information between the host
and the controller. D00 is the LSB of the Even Byte of the Word. D08 is the LSB
of the Odd Byte of the Word.
This signal is the same as the PC Card Memory Mode signal.
In True IDE Mode, all Task File operations occur in byte mode on the low order
bus D[7:0] while all data transfers are 16 bit using D[15:0].
GND
(PC Card Memory Mode)
GND
(PC Card I/O Mode)
GND
(True IDE Mode)
--
1,50
Ground.
This signal is the same for all modes.
This signal is the same for all modes.
Signal Name
Dir.
Pin
Description
-INPACK
(PC Card Memory Mode)
-INPACK
(PC Card I/O Mode)
Input Acknowledge
DMARQ
(True IDE Mode)
O
43
This signal is not used in this mode.
The Input Acknowledge signal is asserted by the CompactFlash Storage Card
when the card is selected and responding to an I/O read cycle at the address
that is on the address bus. This signal is used by the host to control the enable of
any input data buffers between the CompactFlash Storage Card and the CPU.
This signal is a DMA Request that is used for DMA data transfers between host
and device. It shall be asserted by the device when it is ready to transfer data to
or from the host. For Multiword DMA transfers, the direction of data transfer is
controlled by -IORD and -IOWR. This signal is used in a handshake manner with
-DMACK, i.e., the device shall wait until the host asserts -DMACK before
negating DMARQ, and reasserting DMARQ if there is more data to transfer.
DMARQ shall not be driven when the device is not selected.
While a DMA operation is in progress, -CS0 and –CS1 shall be held negated
and the width of the transfers shall be 16 bits.
If there is no hardware support for DMA mode in the host, this output signal is not
used and should not be connected at the host. In this case, the BIOS must report
that DMA mode is not supported by the host so that device drivers will not
attempt DMA mode.
A host that does not support DMA mode and implements both PCMCIA and
True-IDE modes of operation need not alter the PCMCIA mode connections
while in True-IDE mode as long as this does not prevent proper operation in any
mode.


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