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STM32F100V6T6BTR データシート(PDF) 66 Page - STMicroelectronics |
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STM32F100V6T6BTR データシート(HTML) 66 Page - STMicroelectronics |
66 / 84 page Electrical characteristics STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB 66/84 Doc ID 16455 Rev 2 Equation 1: RAIN max formula: Table 41. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply 2.4 3.6 V VREF+ Positive reference voltage 2.4 VDDA V IVREF Current on the VREF input pin 160(1) 220(1) µA fADC ADC clock frequency 0.6 10 MHz fS (2) Sampling rate 0.05 1 MHz fTRIG (2) External trigger frequency fADC = 12 MHz 823 kHz 17 1/fADC VAIN (3) Conversion voltage range 0 (VSSA tied to ground) VREF+ V RAIN (2) External input impedance See Equation 1 and Table 42 for details 50 k RADC (2) Sampling switch resistance 1 k CADC (2) Internal sample and hold capacitor 8pF tCAL (2) Calibration time fADC = 12 MHz 5.9 µs 83 1/fADC tlat (2) Injection trigger conversion latency fADC = 12 MHz 0.214 µs 3(4) 1/fADC tlatr (2) Regular trigger conversion latency fADC = 12 MHz 0.143 µs 2(4) 1/fADC tS (2) Sampling time fADC = 12 MHz 0.125 17.1 µs 1.5 239.5 1/fADC tSTAB (2) Power-up time 0 0 1 µs tCONV (2) Total conversion time (including sampling time) fADC = 12 MHz 1.17 21 µs 14 to 252 (tS for sampling +12.5 for successive approximation) 1/fADC 1. Based on characterization results, not tested in production. 2. Guaranteed by design, not tested in production. 3. In devices delivered in LQFP packages, VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. Devices that come in the TFBGA64 package have a VREF+ pin but no VREF- pin (VREF- is internally connected to VSSA), see Table 4: STM32F100xx pin definitions and Figure 6. 4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 41. R AIN T S f ADC C ADC 2 N2 + ln -------------------------------------------------------------- R ADC – |
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