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STM32F100V6T6B データシート(PDF) 19 Page - STMicroelectronics |
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STM32F100V6T6B データシート(HTML) 19 Page - STMicroelectronics |
19 / 84 page STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Description Doc ID 16455 Rev 2 19/84 pulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages. The TIM2, TIM3, TIM4 general-purpose timers can work together or with the TIM1 advanced-control timer via the Timer Link feature for synchronization or event chaining. TIM2, TIM3, TIM4 all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. Their counters can be frozen in debug mode. TIM15, TIM16 and TIM17 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single channel for input capture/output compare, PWM or one-pulse mode output. The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate with TIM1 via the Timer Link feature for synchronization or event chaining. TIM15 can be synchronized with TIM16 and TIM17. TIM15, TIM16, and TIM17 have a complementary output with dead-time generation and independent DMA request generation Their counters can be frozen in debug mode. 2.16.3 Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base. 2.16.4 Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. 2.16.5 Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. |
同様の部品番号 - STM32F100V6T6B |
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同様の説明 - STM32F100V6T6B |
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