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AM1808AZCED4 データシート(PDF) 45 Page - Texas Instruments |
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AM1808AZCED4 データシート(HTML) 45 Page - Texas Instruments |
45 / 264 page AM1808 www.ti.com SPRS653 – FEBRUARY 2010 3.7.20 Liquid Crystal Display Controller(LCD) Table 3-22. Liquid Crystal Display Controller (LCD) Terminal Functions SIGNAL POWER TYPE(1) PULL(2) DESCRIPTION GROUP(3) NAME NO. VP_DOUT[15] / LCD_D[15] / UPP_XD[7] / GP7[7] / BOOT[7] P4 I/O CP[29] C VP_DOUT[14] / LCD_D[14] / UPP_XD[6] / GP7[6] / BOOT[6] R3 I/O CP[29] C VP_DOUT[13] / LCD_D[13] / UPP_XD[5] / GP7[5] / BOOT[5] R2 I/O CP[29] C VP_DOUT[12] / LCD_D[12] / UPP_XD[4] / GP7[4] / BOOT[4] R1 I/O CP[29] C VP_DOUT[11] / LCD_D[11] / UPP_XD[3] / GP7[3] / BOOT[3] T3 I/O CP[29] C VP_DOUT[10] / LCD_D[10] / UPP_XD[2] / GP7[2] / BOOT[2] T2 I/O CP[29] C VP_DOUT[9] / LCD_D[9] / UPP_XD[1] / GP7[1] / BOOT[1] T1 I/O CP[29] C VP_DOUT[8] / LCD_D[8] / UPP_XD[0] / GP7[0] / BOOT[0] U3 I/O CP[29] C VP_DOUT[7] / LCD_D[7] / UPP_XD[15] / GP7[15] / U2 I/O CP[28] C PRU1_R31[15] LCD data bus VP_DOUT[6] / LCD_D[6] / UPP_XD[14] / GP7[14] / U1 I/O CP[28] C PRU1_R31[14] VP_DOUT[5] / LCD_D[5] / UPP_XD[13] / GP7[13] / V3 I/O CP[28] C PRU1_R31[13] VP_DOUT[4] / LCD_D[4] / UPP_XD[12] / GP7[12] / V2 I/O CP[28] C PRU1_R31[12] VP_DOUT[3] / LCD_D[3] / UPP_XD[11] / GP7[11] / V1 I/O CP[28] C PRU1_R31[11] VP_DOUT[2] / LCD_D[2] / UPP_XD[10] / GP7[10] / W3 I/O CP[28] C PRU1_R31[10] VP_DOUT[1] / LCD_D[1] / UPP_XD[9] / GP7[9] / PRU1_R31[9] W2 I/O CP[28] C VP_DOUT[0] / LCD_D[0] / UPP_XD[8] / GP7[8] / PRU1_R31[8] W1 I/O CP[28] C MMCSD1_DAT[7] / LCD_PCLK / PRU1_R30[7] / GP8[11] F1 O CP[31] C LCD pixel clock MMCSD1_DAT[5] / LCD_HSYNC / PRU1_R30[5] / GP8[9] / H4 O CP[31] C LCD horizontal sync PRU1_R31[6] MMCSD1_DAT[4] / LCD_VSYNC / PRU1_R30[4] / GP8[8] / G4 O CP[31] C LCD vertical sync PRU1_R31[5] LCD AC bias enable chip LCD_AC_ENB_CS / GP6[0]/ / PRU1_R31[28] R5 O CP[31] C select MMCSD1_DAT[6] / LCD_MCLK / PRU1_R30[6] / GP8[10] / F2 O CP[31] C LCD memory clock PRU1_R31[7] (1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Copyright © 2010, Texas Instruments Incorporated Device Overview 45 Submit Documentation Feedback Product Folder Link(s): AM1808 |
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同様の説明 - AM1808AZCED4 |
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