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DAC1408D650 データシート(PDF) 11 Page - NXP Semiconductors

部品番号 DAC1408D650
部品情報  Dual 14-bit DAC, up to 650 Msps, 2쨈 and 4쨈 interpolating with JESD204A interface
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メーカー  NXP [NXP Semiconductors]
ホームページ  http://www.nxp.com
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DAC1408D650_1
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 — 26 May 2009
11 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2
× and 4× interpolating
Ztt
Vtt source impedance
-
0.7
-
∆Zi
differential input
impedance
-
100
-
Digital outputs (SYNC_OUTN/SYNC_OUTP)[3]
Vo(cm)
common-mode output
voltage
C
0.79
0.98
1.46
V
Vo(dif)(p-p)
peak-to-peak
differential output
voltage
C
0.12
0.48
0.96
V
Analog outputs (IOUTAP, IOUTAN, IOUTBP, IOUTBN)
IO(fs)
full-scale output
current
reg value = 00h
D
-
1.6
-
mA
reg = default value
-
20
-
mA
VO
output voltage
compliance range
C
1.8
-
VDDA(3V3) V
Ro
output resistance
D
-
250
-
k
Co
output capacitance
D
-
3
-
pF
NDAC(mono)
DAC monotonicity
guaranteed
D
-
tbd
-
bits
∆EO
offset error variation
C
-
tbd
-
ppm/
°C
∆EG
gain error variation
C
-
tbd
-
ppm/
°C
Reference voltage output (GAPOUT)
VO(ref)
reference output
voltage
I
tbd
1.25
tbd
V
IO(ref)
reference output
current
external voltage 1.2 V
C
-
39
-
µA
∆VO(ref)
reference output
voltage variation
C
-
131
-
ppm/
°C
Analog Auxiliary outputs (AUXAP, AUXAN, AUXBP and AUXBN)
IO(aux)
auxiliary output current differential outputs
I
-
2.2
-
mA
VO(aux)
auxiliary output
voltage
compliance range
C
0
-
2
V
NDAC(aux)mono
auxiliary DAC
monotonicity
guaranteed
D
-
10
-
bits
Input timing (Vin_p / Vin_n)
fdata
data rate
2× interpolation
C
tbd
-
325
Msps
4
× interpolation
tbd
-
162.5
Msps
fbit
bit rate
serial input
tbd
-
3.25
Gbps
Output timing (IOUTAP, IOUTAN, IOUTBP, IOUTBN)
fs
sampling frequency
-
-
650
Msps
ts
settling time
up to 0.5 LSB
D
-
20
-
ns
Table 5.
Characteristics …continued
VDDA(1V8) =VDD(PLL) =VDDD =VDD(IO) = VDD(sintf) = 1.65 V to 1.95 V; VDDA(3V3) = 3.0 V to 3.6 V; AGND, GND(PLL), DGND and
GNDIO are shorted together; Tamb = −40 °C to +85 °C; typical values measured at VDDA(1V8) = VDD(PLL) = VDDD = VDD(IO) =
VDD(sintf) = 1.8 V; VDDA(3V3) = 3.3 V; Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA; maximum sample rate; unless otherwise
specified.
Symbol
Parameter
Conditions
Test[1]
Min
Typ
Max
Unit


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