Si9976DY

Vishay Siliconix

FaxBack 408-970-5600, request 70016

S-60752-Rev. E, 05-Apr-99

www.siliconix.com

3

Notes

a. Refer to PROCESS OPTION FLOWCHART for additional information.

b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.

c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.

d. To supply the output current of 10 mA on a dc basis, an external 13-V supply must be connected between the CAP pin and the S1 pin with the

negative terminal of the supply connected to S1. This is not needed in an actual application because output currents are supplied by the

supply.

f. Internally generated voltage for reference only.

Notes

a. FAULT output retains previous state until ENABLE rising edge.

b. Latch FAULT condition, reset by ENABLE rising edge.

Dynamic

Propogation Delay Time

Low to High Level

G1

350

ns

G2

400

Propogation Delay Time

High to Low Level

G1

150

G2

50

Propogation Delay Time, Low to High

Level, Enable-to-Fault Output

50% IN to FAULT = 2 V, S1 shorted to

GND or V+

500

Output Rise Time (G1, G2)

110

Output Fall Time (G1, G2)

50

Short Circuit Pulse Width

350

TRUTH TABLE

EN

IN

Condition

FAULT OUTPUT

G1 OUT

G2 OUT

1

0

Normal Operation

0

Low

High

1

1

Normal Operation

0

High

Low

0

X

Disabled

Xa

Low

Low

1

0

Load Shorted to V+

1b

Low

Low

11

Load Shorted to

Ground

1b

Low

Low

1

1

0Low

Low

1

0

0

Low

High

X

X

Undervoltage on VDD

c

1Low

Low

Parameter

Symbol

Test Conditions

UnlessOtherwise Specified

V+ = 20 to 40 V

Limits

D Suffix -40 to 85

°C

Unit