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BU1574KU データシート(PDF) 8 Page - Rohm |
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BU1574KU データシート(HTML) 8 Page - Rohm |
8 / 13 page BU1572GUW, BU1573KV, BU1574KU Technical Note 8/12 www.rohm.com 2009.04- Rev.B © 2009 ROHM Co., Ltd. All rights reserved. ●Terminal Layout (BU1572GUW Bottom View) (BU1573KV/BU1574KU Top View) ● Timing Chart 1. I2C interface 1.1 I2C interface timing Table 1.1-1 I2C Interface timing Symbol Parameter MIN. TYP. MAX. Unit fSCL SDC Clock Frequency 0 - 400 kHz tHD;STA Hold-time(repetition)『START』conditions (The first clock pulse is generated after this period.) 0.6 - - us fLOW The "L" period of SDC clock 1.3 - - us tHIGH The "H" period of SDC clock 0.6 - - us tSU;STA Setup time of repetitive 『START』conditions 0.6 - - us tHD;DAT Hold time of SDA 0 - us tSU;DAT Setup time of SDA 100 - - ns tSU;STO Setup time of the 『STOP』conditions 0.6 - - us tBUF Bus free time between『STOP』conditions and the『START』conditions 1.3 - - us tLOW SDA SDC tHD;STA tHD;DAT tHIGH tSU;DAT tSU;STA tHD;ST tSU;STO tBUF 17 LCDDI10 18 LCDDI11 22 LCDDI15 24 LCDDI17 27 VDDIO 29 GND 31 MSEL0/ LCDRS01 33 MSEL2 15 LCDDI8 16 LCDDI9 20 LCDDI13 21 LCDDI14 25 ENAI 30 VDD 32 MSEL1/ LCDRS1I 34 LCDRS0O/ PWMO1 13 LCDDI6 14 LCDDI7 19 LCDDI12 23 LCDDI16 26 VLDI 35 PWMO3/ VLDO 36 ENAO 38 LCDDO1 6 11 LCDDI4 9 LCDDI2 10 LCDDI3 12 LCDDI5 28 DCKI 39 LCDDO1 5 37 LCDDO17/ PWMO2 40 LCDDO1 4 8 LCDDI1 5 LCDWRBI/ SDC 7 LCDDI0 60 RESETB 44 LCDDO1 0 42 LCDDO1 2 41 LCDDO1 3 43 LCDDO1 1 6 LCDDRBI/ I2CDEV0 4 LCDCSBI/ SDA 3 LCDHSI/ LCDRS01 58 SDA/ LCDHSO 55 LCDDO0 51 LCDDO4 46 LCDDO8 45 LCDDO9 64 VDD 62 DCKO 57 LCDCSB O 53 LCDCSB O 52 LCDDO3 48 LCDDO7 47 GND 1 LCDVSI 63 GND 61 VDDIO 59 SDC/ LCDVSO 56 LCDWRBO/ I2CDEV6B 54 LCDDO1 50 LCDDO5 49 LCDDO6 H G F E D C B A 1234567 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VQFP64 (BU1573KV) UQFP64 (BU1574KU) *The terminal arrangement follows terminal function table of P.3-6. |
同様の部品番号 - BU1574KU |
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同様の説明 - BU1574KU |
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