Technical Note

6/17

BU1850MUV

www.rohm.com

2009.09 - Rev.A

© 2009 ROHM Co., Ltd. All rights reserved.

2.

I

Each function of GPIO is controlled by an internal register. The I

register. The device supports up to 400kHz Fast-mode data transfer rate.

2-1

Slave address

Two device addresses (Slave address) can be selected by ADR port.

2-2

Data transfer

One bit of data is transferred during SCL = “1”.

During the bit transfer SCL = “1” cycle, the signal SDA should

keep the value. If SDA changes during SCL = “1”, a START condition or STOP condition occur and it is interpreted

as a control signal.

SDA

SCL

Data is valid

when SDA is

stable

SDA is

variable

Fig.5

Data transfer

2-3

START-STOP-Repeated START conditions

When SDA and SCL are “1”, the data isn’t transferred on the 2-wire bus. If SCL remains “1” and SDA transfers

from “1” to “0”, it means a “Start condition” is occurred and access is started.

If SCL remains “1” and SDA transfers from “0” to “1”, it means a “Stop condition” is occurred and access is

stopped.

It becomes repeated START condition (Sr) the START condition enters again although the STOP condition is not

done.

SDA

SCL

S

Sr

START Condition

Repeated START Condition

P

STOP Condition

Fig.6

START-STOP-Repeated START conditions

A7

A6

A5

A4

A3

A2

A1

R/W

0

0

0

1

0

0

1

1/0

0

0

0

1

1

1

0

ADR=0

ADR=1