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BU4310 データシート(PDF) 5 Page - Rohm

部品番号 BU4310
部品情報  Low Voltage Free Delay Time Setting CMOS Voltage Detector IC Series
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メーカー  ROHM [Rohm]
ホームページ  http://www.rohm.com
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BU4310 データシート(HTML) 5 Page - Rohm

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Technical Note
5/11
BU42□□G series, BU42□□F series, BU42□□FVE series,
BU43□□G series, BU43□□F series, BU43□□FVE series
www.rohm.com
2009.11 - Rev.C
© 2009 ROHM Co., Ltd. All rights reserved.
Setting of Detector Delay Time
This detector IC can be set delay time at the rise of VDD by the capacitor connected to CT terminal.
Delay time at the rise of VDD TPLH:Time until when Vout rise to 1/2 of VDD after VDD rise up and beyond the release
voltage(VDET+∆VDET)
TPLH=-1×CCT×RCT×ln
CCT:
CT pin Externally Attached Capacitance
VCTH:
CT pin Threshold Voltage(P.2 VCTH refer.)
RCT:
CT pin Internal Impedance(P.2 RCT refer.) Ln:
Natural Logarithm
Reference Data of Falling Time (TPHL) Output
Examples of Falling Time (TPHL) Output
Part Number
TPHL [µs]
BU4245G
275.7
BU4345G
359.3
* This data is for reference only.
The figures will vary with the application, so please confirm actual operating conditions before use.
Explanation of Operation
For both the open drain type(Fig.15)and the CMOS output type(Fig.16), the detection and release voltages are used as
threshold voltages. When the voltage applied to the Vdd pins reaches the applicable threshold voltage, the Vout terminal
voltage switches from either “High” to “Low” or from “Low” to “High”. BU42□□G/F/FVE and BU43□□G/F/FVE have delay
time function which set TPLH (Output “Low””High”) using an external capacitor (CCT). Because the BU42□□G/F/FVE
series uses an open drain output type, it is possible to connect a pull-up resistor to VDD or another power supply [The
output “High” voltage (VOUT) in this case becomes VDD or the voltage of the other power supply].
Fig.15 (BU42□□ type internal block diagram)
Fig.16 (BU43□□ type internal block diagram)
Timing Waveforms
Example: the following shows the relationship between the input voltage VDD, the CT Terminal Voltage VCT and the output
voltage VOUT when the input power supply voltage VDD is made to sweep up and sweep down (The circuits are those in
Fig.15 and 16).
When the power supply is turned on, the output is unsettled from
after over the operating limit voltage (VOPL) until TPHL. There fore it is
possible that the reset signal is not outputted when the rise time of
VDD is faster than TPHL.
When VDD is greater than VOPL but less than the reset release
voltage (VDET+∆VDET), the CT terminal (VCT) and output (VOUT)
voltages will switch to L.
If VDD exceeds the reset release voltage (VDET+VDET), then VOUT
switches from L to H (with a delay to the CT terminal).
If VDD drops below the detection voltage (VDET) when the power
supply is powered down or when there is a power supply fluctuation,
VOUT switches to L (with a delay of TPHL).
The potential difference between the detection voltage and the
release voltage is known as the hysteresis width (VDET). The system
is designed such that the output does not flip-flop with power supply
fluctuations within this hysteresis width, preventing malfunctions due
to noise.
VDD-VCTH
VDD
Vref
VDD
GND
CT
R1
R2
R3
Q3
Q1
VOUT
RESET
VDD
Vref
VDD
GND
CT
R1
R2
R3
Q3
Q2
VOUT
RESET
Q1
VDD
VDD
VDET+ΔVDET
VDET
VOPL
0V
1/2 VDD
TPHL
TPLH
TPHL
TPLH
VCT
VOUT
Fig.17


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