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SS811 データシート(PDF) 6 Page - Silicon Standard Corp.

部品番号 SS811
部品情報  Reset Circuits with Manual Reset Input
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メーカー  SSC [Silicon Standard Corp.]
ホームページ  http://www.siliconstandard.com
Logo SSC - Silicon Standard Corp.

SS811 データシート(HTML) 6 Page - Silicon Standard Corp.

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SS811, SS812
Rev.1.01 4/06/2004
BLOCK DIAGRAM
RPULL_UP
20K
R2
R1
MR
GND
RESET
(RESET)
Reset Generator
-
+
Bandgap
VCC
PIN DESCRIPTIONS
GND Pin
:
Ground.
RESET Pin (SS811)
:
Active low output pin. RESET Output remains low while Vcc is below reset threshold.
RESET Pin (SS812)
:
Active high output pin. RESET output remains high while Vcc is below reset threshold.
MR Pin
:
Logic low manual reset input. This active-low input has an internal 20k
pull-up resistor. It can be driven by a TTL or CMOS, or shorted to ground with a switch.
Leave open when unused.
Vcc Pin
:
Supply voltage.
DETAILED DESCRIPTIONS OF TECHNICAL TERMS
RESET OUTPUT
The microprocessor will be activated at a valid reset
state. These
µ P supervisory circuits assert reset to
prevent code execution errors during power-up,
power-down, or brownout conditions.
RESET is guaranteed to be a logic low for
VTH>VCC>0.9V. Once VCC exceeds the reset
threshold, an internal timer keeps RESET low for
the reset timeout period; after this interval, RESET
goes high.
If a brownout condition occurs (VCC drops below the
reset threshold), RESET goes low. Any time VCC
goes below the reset threshold, the internal timer
resets to zero, and RESET goes low. The internal
timer is activated after VCC returns above the reset
threshold, and RESET remains low for the reset
timeout period.
The manual reset input (MR ) can also initiate a
reset. The SS812 has an active-high RESET output
that is the inverse of the SS811’s RESET output.


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