データシートサーチシステム |
|
X1227S8-2.7A データシート(PDF) 10 Page - Xicor Inc. |
|
X1227S8-2.7A データシート(HTML) 10 Page - Xicor Inc. |
10 / 28 page X1227 REV 1.1.20 1/13/03 Characteristics subject to change without notice. 10 of 28 www.xicor.com SERIAL COMMUNICATION Interface Conventions The device supports a bidirectional bus oriented proto- col. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data trans- fers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications. Clock and Data Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 7. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. See Figure 8. Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the Standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. See Figure 8. Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 9. The device will respond with an acknowledge after rec- ognition of a start condition and if the correct Device Identifier and Select bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. The device will acknowledge all incoming data and address bytes, except for: – The Slave Address Byte when the Device Identifier and/or Select bits are incorrect – All Data Bytes of a write when the WEL in the Write Protect Register is LOW – The 2nd Data Byte of a Status Register Write Opera- tion (only 1 data byte is allowed) In the read mode, the device will transmit eight bits of data, release the SDA line, then monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. The device will terminate further data transmissions if an acknowledge is not detected. The master must then issue a stop condition to return the device to Standby mode and place the device into a known state. Figure 6. Reset VTRIP Level Sequence 012 345 67 SCL SDA AEh 0 1 2 345 67 03h RESET VP = 15V 00h 0 1 2 345 67 0 1 2 345 67 00h VCC VCC Note: BP0, BP1, BP2 must be disabled. |
同様の部品番号 - X1227S8-2.7A |
|
同様の説明 - X1227S8-2.7A |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |