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AD9148-M5372-EBZ データシート(PDF) 4 Page - Analog Devices |
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AD9148-M5372-EBZ データシート(HTML) 4 Page - Analog Devices |
4 / 73 page AD9148 Preliminary Technical Data Rev. PrA | Page 4 of 73 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 1. Parameter Min Typ Max Unit RESOLUTION 16 Bits ACCURACY Differential Nonlinearity (DNL) ±2.1 LSB Integral Nonlinearity (INL) ±3.7 LSB MAIN DAC OUTPUTS Offset Error ±0.001 % FSR Gain Error (with Internal Reference) ±2 % FSR Full-Scale Output Current1 8.66 20.2 31.66 mA Output Compliance Range −1.0 +1.0 V Output Resistance 10 MΩ Gain DAC Monotonicity Guaranteed Settling Time to Within ±0.5 LSB 20 ns TEMPERATURE DRIFT Main DAC Offset 0.04 ppm/°C Main DAC Gain 100 ppm/°C Reference Voltage 30 ppm/°C REFERENCE Internal Reference Voltage 1.2 V Output Resistance 5 kΩ ANALOG SUPPLY VOLTAGES AVDD33 3.13 3.3 3.47 V CVDD18 1.71 1.8 1.89 V DIGITAL SUPPLY VOLTAGES IOVDD 1.71 1.8/3.3 3.47 V DVDD18 1.71 1.8 1.89 V POWER CONSUMPTION (NCO OFF, PLL DISABLED, AND SINC−1 FILTER BYPASSED, UNLESS OTHERWISE NOTED) 1 × Mode, fDAC = 300 MSPS, fINTERFACE = 600 MSPS 0.79 W 2 × Mode, fDAC = 500 MSPS, fINTERFACE = 500 MSPS 1.49 W 4 × Mode, fDAC = 800 MSPS, fINTERFACE = 400 MSPS 2.18 W 4 × Mode, fDAC = 800 MSPS, fINTERFACE = 400 MSPS, NCO On 2.47 W 4 × Mode, fDAC = 800 MSPS, fINTERFACE = 400 MSPS, PLL Enabled 2.23 W 4 × Mode, fDAC = 800 MSPS, fINTERFACE = 400 MSPS, Sinc−1 Filter Enabled 2.44 W 8 × Mode, fDAC = 1000 MSPS, fINTERFACE = 250 MSPS 2.48 W Power-Down Mode 0.03 TBD W OPERATING RANGE −40 +25 +85 °C 1 Based on a 10 kΩ external resistor. |
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