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74ABT657 データシート(PDF) 10 Page - NXP Semiconductors |
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74ABT657 データシート(HTML) 10 Page - NXP Semiconductors |
10 / 17 page 74ABT657_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 15 March 2010 10 of 17 NXP Semiconductors 74ABT657 Octal transceiver with parity generator/checker; 3-state VM = 1.5 V Fig 8. 3-state output enable time to LOW-level and output disable time from LOW-level 001aae832 VM VM VOL + 0.3 V VM VI GND tPLZ tPZL OE An, Bn, PARITY, ERROR VOL 3.5 V a. Input pulse definition b. Test circuit Test data and VEXT levels are given in Table 8. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 9. Test circuit for measuring switching times 001aai298 VM VM tW tW 10 % 90 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % 90 % 10 % 10 % tf tr tr tf VEXT VCC VI VO mna616 DUT CL RT RL RL G Table 8. Test data Input Load VEXT VI fI tW tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 3.0 V 1 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω open open 7.0 V |
同様の部品番号 - 74ABT657 |
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同様の説明 - 74ABT657 |
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