74ABT16821A_3

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Product data sheet

Rev. 03 — 16 March 2010

5 of 16

NXP Semiconductors

74ABT16821A

20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state

5.2 Pin description

6.

Functional description

[1]

H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;

↑ = LOW-to-HIGH clock transition;

NC = no change;

X = don’t care;

Z = high-impedance OFF-state.

Table 2.

Pin description

Symbol

Pin

Description

1OE, 2OE

1, 28

output enable input (active LOW)

1Q0 to 1Q9

2, 3, 5, 6, 8, 9, 10, 12, 13, 14

data output

GND

4, 11, 18, 25, 32, 39, 46, 53

ground (0 V)

7, 22, 35, 50

supply voltage

2Q0 to 2Q9

15, 16, 17, 19, 20, 21, 23, 24, 26, 27 data output

2CP, 1CP

29, 56

clock pulse input (active rising edge)

2D0 to 2D9

42, 41, 40, 38, 37, 36, 34, 33, 31, 30 data input

1D0 to1D9

55, 54, 52, 51, 49, 48, 47, 45, 44, 43 data input

Table 3.

Function table[1]

Input

Output

Internal register

Operating mode

nOE

nCP

nDx

nQ0 to nQ9

L

↑

l

L

L

load + read register

L

↑

h

H

H

load + read register

L

H or L

X

NC

NC

hold

H

L or H

X

Z

NC

disable output

H

↑

Dn

Z

Dn

disable output