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74AUP1G11GM データシート(PDF) 10 Page - NXP Semiconductors

部品番号 74AUP1G11GM
部品情報  Low-power 3-input AND gate
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メーカー  NXP [NXP Semiconductors]
ホームページ  http://www.nxp.com
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74AUP1G11GM データシート(HTML) 10 Page - NXP Semiconductors

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74AUP1G11_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 4 September 2007
10 of 16
NXP Semiconductors
74AUP1G11
Low-power 3-input AND gate
[1]
For measuring enable and disable times RL =5kΩ, for measuring propagation delays, setup and hold times and pulse width RL =1MΩ.
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8.
Load circuitry for switching times
001aac521
DUT
RT
VI
VO
VEXT
VCC
RL
5 k
CL
G
Table 10.
Test data
Supply voltage
Load
VEXT
VCC
CL
RL[1]
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
0.8 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF 5 k
Ω or 1 MΩ
open
GND
2
× VCC


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