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74AUP1G38 データシート(PDF) 2 Page - NXP Semiconductors |
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74AUP1G38 データシート(HTML) 2 Page - NXP Semiconductors |
2 / 15 page 74AUP1G38_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 22 June 2009 2 of 15 NXP Semiconductors 74AUP1G38 Low-power 2-input NAND gate (open drain) 3. Ordering information 4. Marking [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G38GW −40 °C to +125 °C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 74AUP1G38GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1.45 × 0.5 mm SOT886 74AUP1G38GF −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1 × 0.5 mm SOT891 Table 2. Marking Type number Marking code[1] 74AUP1G38GW aB 74AUP1G38GM aB 74AUP1G38GF aB Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 001aab717 A Y B 1 2 4 001aab716 4 1 2 & 001aab715 Y GND A B |
同様の部品番号 - 74AUP1G38 |
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同様の説明 - 74AUP1G38 |
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