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74F543 データシート(PDF) 10 Page - NXP Semiconductors |
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74F543 データシート(HTML) 10 Page - NXP Semiconductors |
10 / 15 page 74F543_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 26 January 2010 10 of 15 NXP Semiconductors 74F543 Octal latched transceiver with dual enable; 3-state a. Input pulse definition b. Test circuit Test data is given in Table 8. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 10. Load circuitry for switching times 001aai298 VM VM tW tW 10 % 90 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % 90 % 10 % 10 % tf tr tr tf VEXT VCC VI VO mna616 DUT CL RT RL RL G Table 8. Test data Input Load VEXT VI fI tW tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 3.0 V 1 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω open open 7.0 V |
同様の部品番号 - 74F543 |
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同様の説明 - 74F543 |
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