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74HCT2G126DP データシート(PDF) 8 Page - NXP Semiconductors |
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74HCT2G126DP データシート(HTML) 8 Page - NXP Semiconductors |
8 / 14 page 74HC_HCT2G126_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 24 September 2009 8 of 14 NXP Semiconductors 74HC2G126; 74HCT2G126 Dual buffer/line driver; 3-state Test data is given in Table 10. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 8. Test circuit for measuring switching times VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aad983 DUT VCC VCC VI VO RT RL S1 CL open G Table 10. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74HC2G126 GND to VCC ≤ 6 ns 15 pF, 50 pF 1 k Ω open GND VCC 74HCT2G126 GND to 3 V ≤ 6 ns 15 pF, 50 pF 1 k Ω open GND VCC |
同様の部品番号 - 74HCT2G126DP |
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同様の説明 - 74HCT2G126DP |
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