74LVC1G74DC datasheet(10/21 Pages) NXP

部品番号	74LVC1G74DC

部品情報	Single D-type flip-flop with set and reset; positive edge trigger

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74LVC1G74_8

Product data sheet

Rev. 08 — 3 December 2009

10 of 21

NXP Semiconductors

74LVC1G74

Single D-type ﬂip-ﬂop with set and reset; positive edge trigger

12. Waveforms

Measurement points are given in Table 10.

The shaded areas indicate when the input is permitted to change for predictable output performance.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig 8.

The clock input (CP) to output (Q, Q) propagation delays, the clock pulse width, the D to CP set-up, the

CP to D hold times and the maximum frequency

mnb141

th

tsu

th

tPHL

tPLH

tsu

1/fmax

tW

VM

VI

GND

VM

VI

GND

CP input

D input

VOH

VOL

Q output

VOH

VOL

Q output

Table 10.

Measurement points

Supply voltage

Input

Output

VCC

VM

1.65 V to 1.95 V

0.5

× VCC

0.5

× VCC

2.3 V to 2.7 V

0.5

× VCC

0.5

× VCC

2.7 V

1.5 V

3.0 V to 3.6 V

1.5 V

4.5 V to 5.5 V

0.5

× VCC

0.5

× VCC

同様の部品番号 - 74LVC1G74DC

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同様の説明 - 74LVC1G74DC

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