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74LVC2G00GD データシート(PDF) 1 Page - NXP Semiconductors |
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74LVC2G00GD データシート(HTML) 1 Page - NXP Semiconductors |
1 / 16 page 1. General description The 74LVC2G00 provides a 2-input NAND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features I Wide supply voltage range from 1.65 V to 5.5 V I 5 V tolerant outputs for interfacing with 5 V logic I High noise immunity I ±24 mA output drive (VCC = 3.0 V) I CMOS low power consumption I Complies with JEDEC standard: N JESD8-7 (1.65 V to 1.95 V) N JESD8-5 (2.3 V to 2.7 V) N JESD8-B/JESD36 (2.7 V to 3.6 V) I Latch-up performance exceeds 250 mA I Direct interface with TTL levels I Inputs accept voltages up to 5 V I ESD protection: N HBM JESD22-A114F exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Multiple package options I Specified from −40 °C to +85 °C and −40 °C to +125 °C 74LVC2G00 Dual 2-input NAND gate Rev. 08 — 26 October 2009 Product data sheet |
同様の部品番号 - 74LVC2G00GD |
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同様の説明 - 74LVC2G00GD |
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