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74LVC2G240GM データシート(PDF) 9 Page - NXP Semiconductors |
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74LVC2G240GM データシート(HTML) 9 Page - NXP Semiconductors |
9 / 16 page 74LVC2G240_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 29 February 2008 9 of 16 NXP Semiconductors 74LVC2G240 Dual inverting buffer/line driver; 3-state Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Load circuitry for switching times VEXT VCC VI VO mna616 DUT CL RT RL RL G Table 10. Test data Supply voltage Input Load VEXT VI CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 1.65 V to 1.95 V VCC 30 pF 1 k Ω open GND 2 × VCC 2.3 V to 2.7 V VCC 30 pF 500 Ω open GND 2 × VCC 2.7 V 2.7 V 50 pF 500 Ω open GND 6 V 3.0 V to 3.6 V 2.7 V 50 pF 500 Ω open GND 6 V 4.5 V to 5.5 V VCC 50 pF 500 Ω open GND 2 × VCC |
同様の部品番号 - 74LVC2G240GM |
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同様の説明 - 74LVC2G240GM |
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