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74LVC74A データシート(PDF) 7 Page - NXP Semiconductors

部品番号 74LVC74A
部品情報  Dual D-type flip-flop with set and reset; positive-edge trigger
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メーカー  NXP [NXP Semiconductors]
ホームページ  http://www.nxp.com
Logo NXP - NXP Semiconductors

74LVC74A データシート(HTML) 7 Page - NXP Semiconductors

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74LVC74A_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 4 June 2007
7 of 16
NXP Semiconductors
74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
[4]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
Σ(CL × VCC2 × fo) = sum of the outputs
11. AC waveforms
The shaded areas indicate when the input is permitted to change for predictable output performance.
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V;
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7.
The clock input (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up,
the nCP to nD hold times, and the maximum frequency
mna422
th
tsu
th
tPHL
tPHL
tW
tPLH
tPLH
tsu
1/fmax
VM
VM
VM
VM
VI
GND
VI
GND
nCP input
nD input
VOH
VOL
nQ output
VOH
VOL
nQ output


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