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74LVC245ABQ データシート(PDF) 3 Page - NXP Semiconductors |
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74LVC245ABQ データシート(HTML) 3 Page - NXP Semiconductors |
3 / 17 page 74LVC_LVCH245A_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 25 August 2009 3 of 17 NXP Semiconductors 74LVC245A; 74LVCH245A Octal bus transceiver; 3-state 5. Pinning information 5.1 Pinning 5.2 Pin description (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 3. Pin configuration for SO20 and (T)SSOP20 Fig 4. Pin configuration for DHVQFN20 and DHXQFN20U 74LVC245A 74LVCH245A DIR VCC A0 OE A1 B0 A2 B1 A3 B2 A4 B3 A5 B4 A6 B5 A7 B6 GND B7 001aak292 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 001aak293 74LVC245A 74LVCH245A Transparent top view B6 A6 A7 B5 A5 B4 A4 B3 A3 B2 A2 B1 A1 B0 A0 OE 9 12 8 13 7 14 6 15 5 16 4 17 3 18 2 19 terminal 1 index area GND(1) Table 2. Pin description Symbol Pin Description DIR 1 direction control A0 to A7 2, 3, 4, 5, 6, 7, 8, 9 data input/output GND 10 ground (0 V) B0 to B7 18, 17, 16, 15, 14, 13, 12, 11 data input/output OE 19 output enable input (active LOW) VCC 20 supply voltage |
同様の部品番号 - 74LVC245ABQ |
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同様の説明 - 74LVC245ABQ |
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