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CS4222 データシート(PDF) 5 Page - Cirrus Logic |
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CS4222 データシート(HTML) 5 Page - Cirrus Logic |
5 / 29 page CS4222 DS236F1 5 Pin Name # Pin Description NC 1,14, 15, 28 No Connect - These pins are not connected internally and should be tied to DGND to minimize noise coupling. SMUTE 2 Soft Mute (Input)- Activates a muting function for both the left and right channel D/A converter outputs. Soft muting is achieved by ramping down the volume in 0.5 dB steps until achieving mute if SOFT bit (DAC Control Byte #2) is set to 0 (default). LRCK 4 Left/Right Clock (Input)- Determines which channel is currently being input/output of the serial audio data pins SDIN/SDOUT. The frequency of the Left/Right clock must be equal to the input sample rate. Although the outputs for each ADC channel are transmitted at different times, Left/Right pairs represent simultaneously sampled analog inputs. SCLK 5 Serial Data Clock (Input)- Clocks the individual bits of the serial data into the SDIN pin and out of the SDOUT pin. VD 6 Digital Power (Input)- Positive power supply for the digital section. Nominally 5.0 VDC. DGND 7 Digital Ground (Input)- Digital ground for the digital section. SDOUT 8 Serial Data Output (Output)- Two's complement MSB-first serial data is output on this pin. SDIN 9 Serial Data Input (Input)- Two's complement MSB-first serial data is input on this pin. SCL/CCLK 10 Serial Control Port Clock (Input)- Serial clock for the control port interface. This pin should be tied to DGND in stand-alone mode. SDA/CDIN 11 Serial Control Port Data (Input/Output)- SDAisa data I/O lineinI2C mode and requires an external pull-upresistor accordingtothe I2C specification. CDIN in the input data line for the serial control port in SPI mode. This pin should be tied to DGND in stand-alone mode. AD0/CS 12 Address Bit/Control Chip Select (Input)- In I2C mode, AD0 is a chip address bit. In SPI mode, CS is used to enable the control port interface on the CS4222. The CS4222 will enter SPI mode if a negative transition is ever seen on this pin after power up. This pin should be tied to DGND in stand-alone mode. DEM0 DEM1 13 18 De-emphasis Control (Input) - Selects the standard 15 µs/50µs digital de-emphasis filter response for 32, 44.1 and 48 kHz sample rate. AINR-, AINR+ 16,17 Differential Right Channel Analog Input (Input)- Analog input connections of the right channel differ- ential inputs. Typically 2 Vrms differential (1 Vrms for each input pin) for a fullscale analog input signal. AINL-, AINL+ 19,20 Differential Left Channel Analog Input (Input)- Analog input connections of the left channel differential inputs. Typically 2 Vrms differential (1 Vrms for each input pin) for a fullscale analog input signal. VA 21 Analog Power (Input)- Positive power supply for the analog section. Typically 5.0 VDC. AGND 22 Analog Ground (Input)- Analog ground reference. AOUTR-, AOUTR+ 23, 24 Differential Right Channel Analog Outputs (Output)- The full scale analog output level (differential) is specified in the Analog Characteristics specification table. AOUTL-, AOUTL+ 25, 26 Differential Left Channel Analog Outputs (Output)- The full scale analog output level (differential) is specified in the Analog Characteristics specification table. RST 27 Reset (Input) - When low, the device enters a low power mode and all internal registers are reset, including the control port. When high, the control port becomes operational and normal operation will occur. |
同様の部品番号 - CS4222_02 |
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同様の説明 - CS4222_02 |
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