CS493122-CL datasheet(9/90 Pages) CIRRUS

部品番号	CS493122-CL

部品情報	Multi-Standard Audio Decoder Family

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メーカー	CIRRUS [Cirrus Logic]

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CS49300 Family DSP

DS339F7

9

1.6. Switching Characteristics —

RESET

(VA, VD[3:1] = 2.5 V

±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Notes: 5. The minimum RESET pulse listed above is valid only when using the recommended pull-up/pull-down

resistors on the RD, WR, PSEL and ABOOT mode pins. For Rev. D and older parts, pull-up/pull-down

resistors may be 4.7 k or 3.3 k. For Rev. E and newer parts, pull-up/pull-down resistors must be 3.3 k.

6. This specification is characterized but not production tested.

1.7. Switching Characteristics —

CLKIN

(VA, VD[3:1] = 2.5 V

±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF, PLL Enabled)

Parameter

Symbol

Min

Max

Unit

RESET minimum pulse width low (-CL)

(Note 5)

Trstl

100

-

µs

RESET minimum pulse width low (-IL)

(Note 5)

Trstl

530

-

µs

All bidirectional pins high-Z after RESET low

(Note 6)

Trst2z

-100

ns

Configuration bits setup before RESET high

Trstsu

50

-

ns

Configuration bits hold after RESET high

Trsthld

15

-

ns

RESET

T

rst2z

T

rstl

T

rstsu

T

rsthld

RD, WR,

PSEL, ABOOT

All Bidirectional

Pins

Figure 1. RESET Timing

Parameter

Symbol

Min

Max

Unit

CLKIN period for internal DSP clock mode

Tclki

35

3800

ns

CLKIN high time for internal DSP clock mode

Tclkih

14

-

ns

CLKIN low time for internal DSP clock mode

Tclkil

14

-

ns

CLKIN

Tclkih

Tclkil

Tclki

Figure 2. CLKIN with CLKSEL = VSS = PLL Enable

同様の部品番号 - CS493122-CL

メーカー	部品番号	データシート	部品情報
Cirrus Logic	CS493122-CL	1Mb / 86P	Multi-Standard Audio Decoder Family

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