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FAN103 データシート(PDF) 11 Page - Fairchild Semiconductor

部品番号 FAN103
部品情報  Primary-Side-Regulation PWM Controller (PWM-PSR)
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メーカー  FAIRCHILD [Fairchild Semiconductor]
ホームページ  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FAN103 データシート(HTML) 11 Page - Fairchild Semiconductor

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© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN103 • Rev. 1.0.3
11
Cable Voltage Drop Compensation
When it comes to cellular phone charger applications,
the battery is located at the end of cable, which causes,
typically, several percentage of voltage drop on the
actual battery voltage. FAN103 has a built-in cable
voltage drop compensation, which provides a constant
output voltage at the end of the cable over the entire
load range in CV mode. As load increases, the voltage
drop across the cable is compensated by increasing the
reference voltage of voltage regulation error amplifier.
Operating Current
The operating current in FAN103 is as small as 3.2mA.
The small operating current results in higher efficiency
and reduces the VDD hold-up capacitance requirement.
Once FAN103 enters deep-green mode, the operating
current is reduced to 0.95mA, assisting the power
supply in meeting power conservation requirements.
Green-Mode Operation
The FAN103 uses voltage regulation error amplifier
output (VCOMV) as an indicator of the output load and
modulates the PWM frequency, as shown in Figure 23.
The switching frequency decreases as load decreases.
In heavy load conditions, the switching frequency is
fixed at 50kHz. Once VCOMV decreases below 2.5V, the
PWM frequency linearly decreases from 50kHz. When
FAN103 enters into deep-green mode, the PWM
frequency is reduced to a minimum frequency of 370Hz,
gaining power saving to help meet international power
conservation requirements.
Figure 23. Switching Frequency in Green Mode
Frequency Hopping
EMI reduction is accomplished by frequency hopping,
which spreads the energy over a wider frequency range
than the bandwidth measured by the EMI test
equipment. FAN103 has an internal frequency hopping
circuit that changes the switching frequency between
47kHz and 53kHz with a period, as shown in Figure 24.
Figure 24. Frequency Hopping
High-Voltage Startup
Figure 25 shows the HV-startup circuit for FAN103
applications. The HV pin is connected to the line input or
bulk capacitor through a resistor, RSTART (100kΩ is
recommended). During startup, the internal startup
circuit in FAN103 is enabled. Meanwhile, line input
supplies the current, ISTARTUP, to charge the hold-up
capacitor, CDD, through RSTART. When the VDD voltage
reaches VDD-ON, the internal startup circuit is disabled,
blocking ISTARTUP from flowing into the HV pin. Once the
IC turns on, CDD is the only energy source to supply the
IC consumption current before the PWM starts to
switch. Thus, CDD must be large enough to prevent VDD
from dropping to VDD-OFF before the power can be
delivered from the auxiliary winding.
Figure 25. HV Startup Circuit


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