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TDA8933T データシート(PDF) 7 Page - NXP Semiconductors |
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TDA8933T データシート(HTML) 7 Page - NXP Semiconductors |
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7 / 47 page  TDA8933_1 © NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 01 — 15 May 2007 7 of 47 NXP Semiconductors TDA8933 Class-D audio amplifier 8.2 Mode selection and interfacing The TDA8933 can be switched to one of four operating modes using pins POWERUP and ENGAGE: • Sleep mode: with low supply current • Mute mode: the amplifiers are switching idle (50 % duty cycle), but the audio signal at the output is suppressed by disabling the Vl-converter input stages. The capacitors on pins HVP1 and HVP2 have been charged to half the supply voltage (asymmetrical supply only) • Operating mode: the amplifiers are fully operational with an output signal • Fault mode Both pins POWERUP and ENGAGE refer to pin CGND. Table 4 shows the different modes as a function of the voltages on the POWERUP and ENGAGE pins. [1] When there are symmetrical supply conditions, the voltage applied to pins POWERUP and ENGAGE must never exceed the supply voltage (VDDA, VDDP1 or VDDP2). If the transition between Mute mode and Operating mode is controlled via a time constant, the start-up will be pop free since the DC output offset voltage is applied gradually to the output between Mute mode and Operating mode. The bias current setting of the VI-converters is related to the voltage on pin ENGAGE. • Mute mode: the bias current setting of the VI-converters is zero (VI-converters disabled). • Operating mode: the bias current is at maximum. The time constant required to apply the DC output offset voltage gradually between Mute mode and Operating mode can be generated by applying a decoupling capacitor on pin ENGAGE. The value of the capacitor on pin ENGAGE should be 470 nF. Table 4. Mode selection for the TDA8933 Mode Pin POWERUP[1] ENGAGE[1] DIAG Sleep < 0.8 V < 0.8 V undefined Mute 2 V to 6 V < 0.8 V > 2 V Operating 2 V to 6 V 3 V to 6 V > 2 V Fault 2 V to 6 V undefined < 0.8 V |
同様の部品番号 - TDA8933T |
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同様の説明 - TDA8933T |
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