ADM1033

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10

SMBus 2.0 Fixed and Discoverable Mode

The ADM1033 also supports fixed and discoverable mode,

which is backwards compatible with SMBus 1.0 and 1.1.

Fixed and discoverable mode supports all the same

functionality as ARP−capable mode, except for assign

address in which case it powers up with a fixed address and

is not changed by the assign address call. The fixed address

is determined by the state of the LOCATION pin on powerup.

SMBus 2.0 Read and Write Operations

The master initiates data transfer by establishing a start

condition, defined as a high−to−low transition on the serial

data line (SDA) while the serial clock line (SCL) remains

high. This indicates that an address/data stream is to follow.

All slave peripherals connected to the serial bus respond to

the start condition and shift in the next 8 bits, which consist

of a 7−bit address (MSB first) plus an R/W bit. This last bit

determines the direction of the data transfer (whether data is

written to or read from the slave device).

1. The peripheral that corresponds to the transmitted

address responds by pulling the data line low

during the low period before the 9th clock pulse,

which is known as the acknowledge bit. All other

devices on the bus remain idle while the selected

device waits for data to be read from or written to

it. If the R/W bit is a 0, the master writes to the

slave device. If the R/W bit is a 1, the master reads

from it.

2. Data is sent over the serial bus in sequences of 9

clock pulses − 8 bits of data followed by an

acknowledge bit from the slave device. Transitions

on the data line must occur during the low period

of the clock signal and remain stable during the

high period, because a low−to−high transition

when the clock is high may be interpreted as a stop

signal. The number of data bytes that can be

transmitted over the serial bus in a single read or

write operation is limited only by what the master

and slave devices can handle.

3. When all data bytes have been read or written,

stop conditions are established. In write mode, the

master pulls the data line high during the 10th

clock pulse to assert a stop condition. In read

mode, the master device overrides the

acknowledge bit by pulling the data line high

during the low period before the 9th clock pulse.

This is known as no acknowledge. The master

takes the data line low during the low period

before the 10th clock pulse, then high during the

10th clock pulse to assert a stop condition.

It is not possible to mix read and write in one operation,

because the type of operation is determined at the beginning

and cannot be changed without starting a new operation.

To write data to one of the device data registers or to read

data from it, the address pointer register (APR) must be set

so that the correct data register is addressed; then data can be

written into that register or read from it. The first byte of a

write operation always contains an address that is stored in

the APR. If data is to be written to the device, then the write

operation contains a second data byte, which is written to the

register selected by the APR.

As illustrated in Figure 17, the device address is sent over

the bus, followed by R/W set to 0. This is followed by two

data bytes. The first data byte is the address of the internal

data register to be written to, which is stored in the APR. The

second data byte is the data to be written to the internal data

register.

When reading data from a register there are two

possibilities.

If the ADM1033’s APR value is unknown or incorrect, it

must be set to the correct value before data can be read from

the desired data register. To do this, perform a write to the

ADM1033 as before, but send only the data byte containing

the register. (See Figure 18.) A read operation is then

performed, using the serial bus address and the R/W bit set

to 1, followed by the data byte read from the data register.

(See Figure 19.)

However, if the APR is already at the desired address, data

can be read from the corresponding data register without first

writing to the APR. In this case, See Figure 18 can be omitted.

In Figure 17 to Figure 19, the serial bus address is

determined by the state of the LOCATION pin on powerup.

Figure 17. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register

START BY

MASTER

STOP BY

MASTER

ACK. BY

ADM1033

ACK. BY

ADM1033

ACK. BY

ADM1033

A6

11

9

9

A5

A4

A3

A2

A1

A0

R/W

D7

D6

D5

D4

D3

D2

D1

D0

SCL

SDA

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

FRAME 3

DATA BYTE

SDA (CONTINUED)

SCL (CONTINUED)

9

1

D7

D6

D5

D4

D3

D2

D1

D0