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MC14015B データシート(PDF) 1 Page - Motorola, Inc |
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MC14015B データシート(HTML) 1 Page - Motorola, Inc |
1 / 8 page MOTOROLA CMOS LOGIC DATA 57 MC14015B Dual 4-Bit Static Shift Register The MC14015B dual 4–bit static shift register is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. It consists of two identical, independent 4–state serial–input/parallel–output registers. Each register has independent Clock and Reset inputs with a single serial Data input. The register states are type D master–slave flip–flops. Data is shifted from one stage to the next during the positive–going clock transition. Each register can be cleared when a high level is applied on the Reset line. These complementary MOS shift registers find primary use in buffer storage and serial–to–parallel conversion where low power dissipation and/or noise immunity is desired. • Diode Protection on All Inputs • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Logic Edge–Clocked Flip–Flop Design — Logic state is retained indefinitely with clock level either high or low; information is transferred to the output only on the positive going edge of the clock pulse. • Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range. MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD DC Supply Voltage – 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V lin, lout Input or Output Current (DC or Transient), per Pin ± 10 mA PD Power Dissipation, per Package† 500 mW Tstg Storage Temperature – 65 to + 150 _C TL Lead Temperature (8–Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/ _C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/ _C From 100_C To 125_C TRUTH TABLE C D R Q0 Qn 0 0 0 Qn–1 1 0 1 Qn–1 X 0 No Change No Change X X 1 0 0 X = Don’t Care Qn = Q0, Q1, Q2, or Q3, as applicable. Qn–1 = Output of prior stage. MOTOROLA SEMICONDUCTOR TECHNICAL DATA © Motorola, Inc. 1995 REV 3 1/94 MC14015B L SUFFIX CERAMIC CASE 620 ORDERING INFORMATION MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBD SOIC TA = – 55° to 125°C for all packages. P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B BLOCK DIAGRAM 14 1 15 6 9 7 5 4 3 10 13 12 11 2 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 D C R R D C VDD = PIN 16 VSS = PIN 8 |
同様の部品番号 - MC14015B |
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同様の説明 - MC14015B |
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