CAT24AA04, CAT24AA08

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5

Figure 4. Acknowledge Timing

18

9

START

SCL FROM

MASTER

BUS RELEASE DELAY (TRANSMITTER)

BUS RELEASE DELAY (RECEIVER)

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

Figure 5. Bus Timing

SCL

SDA IN

SDA OUT

WRITE OPERATIONS

Byte Write

To write data to memory, the Master creates a START

condition on the bus and then broadcasts a Slave address

with the R/W bit set to ‘0’. The Master then sends an address

byte and a data byte and concludes the session by creating

a STOP condition on the bus. The Slave responds with ACK

after every byte sent by the Master (Figure 6). The STOP

starts the internal Write cycle, and while this operation is in

does not acknowledge the Master (Figure 7).

Page Write

The Byte Write operation can be expanded to Page Write,

by sending more than one data byte to the Slave before

issuing the STOP condition (Figure 8). Up to 16 distinct data

bytes can be loaded into the internal Page Write Buffer

starting at the address provided by the Master. The page

address is latched, and as long as the Master keeps sending

data, the internal byte address is incremented up to the end

of page, where it then wraps around (within the page). New

data can therefore replace data loaded earlier. Following the

STOP, data loaded during the Page Write session will be

Acknowledge Polling

The acknowledge (ACK) polling routine can be used to

take advantage of the typical write cycle time. Once the stop

condition is issued to indicate the end of the host’s write

operation, the CAT24AA04/08 initiates the internal write

cycle. The ACK polling can be initiated immediately. This

involves issuing the start condition followed by the slave

address for a write operation. If the CAT24AA04/08 is still

busy with the write operation, NoACK will be returned. If

the CAT24AA04/08 device has completed the internal write

operation, an ACK will be returned and the host can then

proceed with the next read or write operation.

Hardware Write Protection

With the WP pin held HIGH, the entire memory is

protected against Write operations. If the WP pin is left

floating or is grounded, it has no impact on the Write

operation. The state of the WP pin is strobed on the last

(Figure 9). If the WP pin is HIGH during the strobe interval,

the Slave will not acknowledge the data byte and the Write

request will be rejected.

Delivery State

The CAT24AA04/08 is shipped erased, i.e., all bytes are FFh.