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CAT24C03YI-T3 データシート(PDF) 6 Page - ON Semiconductor |
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CAT24C03YI-T3 データシート(HTML) 6 Page - ON Semiconductor |
6 / 14 page CAT24C03, CAT24C05 http://onsemi.com 6 WRITE OPERATIONS Byte Write In Byte Write mode, the Master sends the START condition and the Slave address with the R/W bit set to zero to the Slave. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the CAT24C03/05. After receiving another acknowledge from the Slave, the Master transmits the data byte to be written into the addressed memory location. The CAT24C03/05 device will acknowledge the data byte and the Master generates the STOP condition, at which time the device begins its internal Write cycle to nonvolatile memory (Figure 6). While this internal cycle is in progress (tWR), the SDA output will be tri−stated and the CAT24C03/05 will not respond to any request from the Master device (Figure 7). Page Write The CAT24C03/05 writes up to 16 bytes of data in a single write cycle, using the Page Write operation (Figure 8). The Page Write operation is initiated in the same manner as the Byte Write operation, however instead of terminating after the data byte is transmitted, the Master is allowed to send up to fifteen additional bytes. After each byte has been transmitted the CAT24C03/05 will respond with an acknowledge and internally increments the four low order address bits. The high order bits that define the page address remain unchanged. If the Master transmits more than sixteen bytes prior to sending the STOP condition, the address counter ‘wraps around’ to the beginning of page and previously transmitted data will be overwritten. Once all sixteen bytes are received and the STOP condition has been sent by the Master, the internal Write cycle begins. At this point all received data is written to the CAT24C03/05 in a single write cycle. Acknowledge Polling The acknowledge (ACK) polling routine can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation, the CAT24C03/05 initiates the internal write cycle. The ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAT24C03/05 is still busy with the write operation, NoACK will be returned. If the CAT24C03/05 has completed the internal write operation, an ACK will be returned and the host can then proceed with the next read or write operation. Hardware Write Protection With the WP pin held HIGH, the upper half of memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the operation of the CAT24C03/05. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the first data byte (Figure 9). If the WP pin is HIGH during the strobe interval, the CAT24C03/05 will not acknowledge the data byte and the Write request will be rejected. Delivery State The CAT24C03/05 is shipped erased, i.e., all bytes are FFh. ADDRESS BYTE DATA BYTE SLAVE ADDRESS S A C K A C K A C K S T O P P S T A R T BUS ACTIVITY: MASTER SLAVE Figure 6. Byte Write Sequence a7 ÷ a0 d7 ÷ d0 |
同様の部品番号 - CAT24C03YI-T3 |
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同様の説明 - CAT24C03YI-T3 |
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