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CAT24WC66XE-1.8-T3C データシート(PDF) 3 Page - ON Semiconductor |
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CAT24WC66XE-1.8-T3C データシート(HTML) 3 Page - ON Semiconductor |
3 / 11 page CAT24WC66 http://onsemi.com 3 Table 5. A.C. CHARACTERISTICS (VCC = 1.8 V to 5.5 V, unless otherwise specified. Output Load is 1TTL Gate and 100 pF.) Symbol Parameter 1.8 V − 2.5 V 4.5 V − 5.5 V Units Min Max Min Max MEMORY READ & WRITE CYCLE LIMITS FSCL Clock Frequency 100 400 kHz TI (Note 6) Noise Suppression Time Constant at SCL, SDA Inputs 200 200 ns tAA SCL Low to SDA Data Out and ACK Out 3.5 1 ms tBUF (Note 6) Time the Bus Must be Free Before a New Transmission Can Start 4.7 1.2 ms tHD:STA Start Condition Hold Time 4 0.6 ms tLOW Clock Low Period 4.7 1.2 ms tHIGH Clock High Period 4 0.6 ms tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 4.7 0.6 ms tHD:DAT Data In Hold Time 0 0 ns tSU:DAT Data In Setup Time 50 50 ns tR (Note 6) SDA and SCL Rise Time 1 0.3 ms tF (Note 6) SDA and SCL Fall Time 300 300 ns tSU:STO Stop Condition Setup Time 4 0.6 ms tDH Data Out Hold Time 100 100 ns 6. This parameter is tested initially and after a design or process change that affects the parameter. Table 6. POWER−UP TIMING (Notes 6, 7) Symbol Parameter Min Typ Max Units tPUR Power−Up to Read Operation 1 ms tPUW Power−Up to Write Operation 1 ms 7. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. Table 7. WRITE CYCLE LIMITS Symbol Parameter Min Typ Max Units tWR Write Cycle Time 10 ms The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. |
同様の部品番号 - CAT24WC66XE-1.8-T3C |
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同様の説明 - CAT24WC66XE-1.8-T3C |
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