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CAT150021LWI-GT3 データシート(PDF) 7 Page - ON Semiconductor |
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CAT150021LWI-GT3 データシート(HTML) 7 Page - ON Semiconductor |
7 / 15 page CAT15002, CAT15004 © 2008 SCILLC. All rights reserved. 7 Doc. No. MD-1126 Rev. B Characteristics subject to change without notice STATUS REGISTER The Status Register, as shown in Table 2, contains a number of status and control bits. The RDY ¯¯¯¯ (Ready) bit indicates whether the device is busy with a write operation. This bit is automatically set to 1 during an internal write cycle, and reset to 0 when the device is ready to accept commands. For the host, this bit is read only. The WEL (Write Enable Latch) bit is set/reset by the WREN/WRDI commands. When set to 1, the device is in a Write Enable state and when set to 0, the device is in a Write Disable state. The BP0 and BP1 (Block Protect) bits determine which blocks are currently write protected. They are set by the user with the WRSR command and are non-volatile. The user is allowed to protect a quarter, one half or the entire memory, by setting these bits according to Table 3. The protected blocks then become read-only. Table 2. Status Register 7 6 5 4 3 2 1 0 1 1 1 1 BP1 BP0 WEL RDY ¯¯¯¯ Table 3. Block Protection Bits Status Register Bits BP1 BP0 Array Address Protected Protection 0 0 None No Protection 15002: C0-FF 0 1 15004: 180-1FF Quarter Array Protection 15002: 80-FF 1 0 15004: 100-1FF Half Array Protection 15002: 00-FF 1 1 15004: 000-1FF Full Array Protection |
同様の部品番号 - CAT150021LWI-GT3 |
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同様の説明 - CAT150021LWI-GT3 |
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