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CAT150161TWI-GT3 データシート(PDF) 5 Page - ON Semiconductor |
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CAT150161TWI-GT3 データシート(HTML) 5 Page - ON Semiconductor |
5 / 15 page CAT15008, CAT15016 © 2008 SCILLC. All rights reserved. 5 Doc. No. MD-1125 Rev. B Characteristics subject to change without notice PIN DESCRIPTION RESET/RESET ¯¯¯¯¯¯: Reset output is available in two versions: CMOS Active Low (CAT150xx9) and CMOS Active High (CAT150xx1). Both versions are push-pull outputs for high efficiency. SI: The serial data input pin accepts op-codes, addresses and data. In SPI modes (0,0) and (1,1) input data is latched on the rising edge of the SCK clock input. SO: The serial data output pin is used to transfer data out of the device. In SPI modes (0,0) and (1,1) data is shifted out on the falling edge of the SCK clock. SCK: The serial clock input pin accepts the clock provided by the host and used for synchronizing communication between host and CAT15008/16. CS ¯¯ : The chip select input pin is used to enable/disable the CAT15008/16. When CS ¯¯ is high, the SO output is tri-stated (high impedance) and the device is in Standby Mode (unless an internal write operation is in progress). Every communication session between host and CAT15008/16 must be preceded by a high to low transition and concluded with a low to high transition of the CS ¯¯ input. WP ¯¯¯: The write protect input pin will allow all write operations to the device when held high. When WP ¯¯¯ pin is tied low and the WPEN bit in the Status Register (refer to Status Register description, later in this Data Sheet) is set to “1”, writing to the Status Register is disabled. DEVICE OPERATION The CAT15008/16 products combine the accurate voltage monitoring capabilities of a standalone voltage supervisor with the high quality and reliability of standard EEPROMs from Catalyst Semiconductor. RESET CONTROLLER DESCRIPTION The reset signal is asserted LOW for the CAT150xx9 and HIGH for the CAT150xx1 when the power supply voltage falls below the threshold trip voltage and remains asserted for at least 140ms (tPURST) after the power supply voltage has risen above the threshold. Reset output timing is shown in Figure 1. The CAT15008/16 devices protect µPs against brown-out failure. Short duration VCC transients of 4µsec or less and 100mV amplitude typically do not generate a Reset pulse. VCC PURST t PURST t RPD t RVALID V V TH RESE T RESE T CAT150xx9 CAT150xx1 RPD t Figure 1. RESET Output Timing |
同様の部品番号 - CAT150161TWI-GT3 |
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同様の説明 - CAT150161TWI-GT3 |
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