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N01L63W2AT25I データシート(PDF) 2 Page - ON Semiconductor |
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N01L63W2AT25I データシート(HTML) 2 Page - ON Semiconductor |
2 / 10 page Rev. 9 | Page 2 of 10 | www.onsemi.com N01L63W2A Functional Block Diagram Functional Description CE1 CE2 WE OE UB LB I/O0 - I/O151 1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7 are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown. MODE POWER H X XX XX High Z Standby2 2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally isolated from any external influence and disabled from exerting any influence externally. Standby X L XX XX High Z Standby2 Standby L H X X H H High Z Standby Standby LHL X3 3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit. L1 L1 Data In Write3 Active LH HL L1 L1 Data Out Read Active LH H H L1 L1 High Z Active Active Capacitance1 1. These parameters are verified in device characterization and are not 100% tested Item Symbol Test Condition Min Max Unit Input Capacitance CIN VIN = 0V, f = 1 MHz, TA = 25oC 8pF I/O Capacitance CI/O VIN = 0V, f = 1 MHz, TA = 25oC 8pF Address Inputs A0 - A3 Address Inputs A4 - A15 Word Address Decode Logic 4K Page x 16 word x 16 bit RAM Array Input/ Output Mux and Buffers Page Address Decode Logic Control Logic CE1 CE2 WE OE UB LB I/O0 - I/O7 I/O8 - I/O15 |
同様の部品番号 - N01L63W2AT25I |
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同様の説明 - N01L63W2AT25I |
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