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TMP513AID データシート(PDF) 3 Page - Texas Instruments

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部品番号 TMP513AID
部品情報  Temperature and Power Supply System Monitors
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
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TMP513AID データシート(HTML) 3 Page - Texas Instruments

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TMP512
TMP513
www.ti.com
SBOS491 – JUNE 2010
THERMAL INFORMATION
TMP513AIRSAR
TMP512
TMP513AID
TMP513AIRSAT
THERMAL METRIC(1)
UNITS
D (SOIC)
D (SOIC)
RSA
14
16
16
qJA
Junction-to-ambient thermal resistance(2)
91.1
77.6
44.8
qJC(top)
Junction-to-case(top) thermal resistance(3)
10.6
55.0
43.8
qJB
Junction-to-board thermal resistance(4)
40.3
49.9
14.7
°C/W
yJT
Junction-to-top characterization parameter(5)
49.1
3.5
0.4
yJB
Junction-to-board characterization parameter(6)
47.5
32.2
14.5
qJC(bottom)
Junction-to-case(bottom) thermal resistance(7)
n/a
n/a
2.6
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2010, Texas Instruments Incorporated
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