SN74AUP1G74DCUR datasheet(4/24 Pages) TI

部品番号	SN74AUP1G74DCUR

部品情報	LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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SN74AUP1G74

SCES644C – MARCH 2006 – REVISED MARCH 2010

www.ti.com

RECOMMENDED OPERATING CONDITIONS

(1)

MIN

MAX

UNIT

VCC

Supply voltage

0.8

3.6

V

VCC = 0.8 V

VCC

VCC = 1.1 V to 1.95 V

0.65 × VCC

VIH

High-level input voltage

V

VCC = 2.3 V to 2.7 V

1.6

VCC = 3 V to 3.6 V

2

VCC = 0.8 V

0

VCC = 1.1 V to 1.95 V

0.35 × VCC

VIL

Low-level input voltage

V

VCC = 2.3 V to 2.7 V

0.7

VCC = 3 V to 3.6 V

0.9

VI

Input voltage

0

3.6

V

VO

Output voltage

0

VCC

V

VCC = 0.8 V

–20

mA

VCC = 1.1 V

–1.1

VCC = 1.4 V

–1.7

IOH

High-level output current

VCC = 1.65

–1.9

mA

VCC = 2.3 V

–3.1

VCC = 3 V

–4

VCC = 0.8 V

20

mA

VCC = 1.1 V

1.1

VCC = 1.4 V

1.7

IOL

Low-level output current

VCC = 1.65 V

1.9

mA

VCC = 2.3 V

3.1

VCC = 3 V

4

Δt/Δv

Input transition rise or fall rate

VCC = 0.8 V to 3.6 V

200

ns/V

TA

Operating free-air temperature

–40

85

°C

(1)

All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

4

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Product Folder Link(s): SN74AUP1G74

同様の部品番号 - SN74AUP1G74DCUR

メーカー	部品番号	データシート	部品情報
Texas Instruments	SN74AUP1G74DCUR	258Kb / 17P	[Old version datasheet] LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
	SN74AUP1G74DCUR	1Mb / 31P	[Old version datasheet] Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop
	SN74AUP1G74DCURG4	258Kb / 17P	[Old version datasheet] LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
	SN74AUP1G74DCURG4	1Mb / 31P	[Old version datasheet] Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop

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同様の説明 - SN74AUP1G74DCUR

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