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SN74AVCH8T245PWR データシート(PDF) 2 Page - Texas Instruments |
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SN74AVCH8T245PWR データシート(HTML) 2 Page - Texas Instruments |
2 / 22 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) DIR OE A1 B1 To Seven Other Channels 2 3 22 21 SN74AVCH8T245 8-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES565G – APRIL 2004 – REVISED MARCH 2007 The SN74AVCH8T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated. The SN74AVCH8T245 is designed so the control pins (DIR and OE) are supplied by VCCA. The SN74AVCH8T245 solution is compatible with a single-supply system and can be replaced later with a '245 function, with minimal printed circuit board redesign. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, both outputs are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (each 8-bit section) INPUTS OPERATION OE DIR L L B data to A bus L H A data to B bus H X All output Hi-Z LOGIC DIAGRAM (POSITIVE LOGIC) 2 Submit Documentation Feedback |
同様の部品番号 - SN74AVCH8T245PWR |
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同様の説明 - SN74AVCH8T245PWR |
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