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LM3S9790-EQC25-C1T データシート(PDF) 11 Page - Texas Instruments |
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LM3S9790-EQC25-C1T データシート(HTML) 11 Page - Texas Instruments |
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11 / 1185 page  List of Figures Figure 1-1. Stellaris ® LM3S9790 Microcontroller High-Level Block Diagram ............................. 66 Figure 2-1. CPU Block Diagram ............................................................................................. 69 Figure 2-2. TPIU Block Diagram ............................................................................................ 77 Figure 5-1. JTAG Module Block Diagram ................................................................................ 88 Figure 5-2. Test Access Port State Machine ........................................................................... 91 Figure 5-3. IDCODE Register Format ..................................................................................... 97 Figure 5-4. BYPASS Register Format .................................................................................... 97 Figure 5-5. Boundary Scan Register Format ........................................................................... 98 Figure 6-1. Basic RST Configuration .................................................................................... 101 Figure 6-2. External Circuitry to Extend Power-On Reset ....................................................... 102 Figure 6-3. Reset Circuit Controlled by Switch ...................................................................... 102 Figure 6-4. Power Architecture ............................................................................................ 105 Figure 6-5. Main Clock Tree ................................................................................................ 108 Figure 7-1. Hibernation Module Block Diagram ..................................................................... 204 Figure 7-2. Using a Crystal as the Hibernation Clock Source ................................................. 207 Figure 7-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON Mode ................................................................................................................ 207 Figure 8-1. Internal Memory Block Diagram .......................................................................... 230 Figure 9-1. μDMA Block Diagram ......................................................................................... 268 Figure 9-2. Example of Ping-Pong μDMA Transaction ........................................................... 274 Figure 9-3. Memory Scatter-Gather, Setup and Configuration ................................................ 276 Figure 9-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 277 Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 279 Figure 9-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 280 Figure 10-1. Digital I/O Pads ................................................................................................. 330 Figure 10-2. Analog/Digital I/O Pads ...................................................................................... 331 Figure 10-3. GPIODATA Write Example ................................................................................. 332 Figure 10-4. GPIODATA Read Example ................................................................................. 332 Figure 11-1. EPI Block Diagram ............................................................................................. 383 Figure 11-2. SDRAM Non-Blocking Read Cycle ...................................................................... 390 Figure 11-3. SDRAM Normal Read Cycle ............................................................................... 391 Figure 11-4. SDRAM Write Cycle ........................................................................................... 392 Figure 11-5. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 1, RDHIGH = 1 .......................... 399 Figure 11-6. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 1, RDHIGH = 1 .......................... 399 Figure 11-7. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH = 1, RDHIGH = 1 ............................................................................................... 400 Figure 11-8. Continuous Read Mode Accesses ...................................................................... 400 Figure 11-9. Write Followed by Read to External FIFO ............................................................ 401 Figure 11-10. Two-Entry FIFO ................................................................................................. 401 Figure 11-11. Single-Cycle Write Access, FRM50=0, FRMCNT=0, WRCYC=0 ........................... 405 Figure 11-12. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, RDCYC=1, WRCYC=1 ........................................................................................................ 405 Figure 11-13. Read Accesses, FRM50=0, FRMCNT=0, RDCYC=1 ............................................ 406 Figure 11-14. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 406 Figure 11-15. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 406 Figure 11-16. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 407 11 June 14, 2010 Texas Instruments-Advance Information Stellaris® LM3S9790 Microcontroller |
同様の部品番号 - LM3S9790-EQC25-C1T |
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同様の説明 - LM3S9790-EQC25-C1T |
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