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LM3S9790-EQR80-C1 データシート(PDF) 4 Page - Texas Instruments |
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LM3S9790-EQR80-C1 データシート(HTML) 4 Page - Texas Instruments |
4 / 1185 page 5.5.1 Instruction Register (IR) ................................................................................................. 95 5.5.2 Data Registers .............................................................................................................. 97 6 System Control ....................................................................................................... 99 6.1 Signal Description ......................................................................................................... 99 6.2 Functional Description ................................................................................................... 99 6.2.1 Device Identification .................................................................................................... 100 6.2.2 Reset Control .............................................................................................................. 100 6.2.3 Non-Maskable Interrupt ............................................................................................... 104 6.2.4 Power Control ............................................................................................................. 105 6.2.5 Clock Control .............................................................................................................. 105 6.2.6 System Control ........................................................................................................... 112 6.3 Initialization and Configuration ..................................................................................... 114 6.4 Register Map .............................................................................................................. 114 6.5 Register Descriptions .................................................................................................. 115 7 Hibernation Module .............................................................................................. 203 7.1 Block Diagram ............................................................................................................ 204 7.2 Signal Description ....................................................................................................... 204 7.3 Functional Description ................................................................................................. 205 7.3.1 Register Access Timing ............................................................................................... 206 7.3.2 Hibernation Clock Source ............................................................................................ 206 7.3.3 Battery Management ................................................................................................... 208 7.3.4 Real-Time Clock .......................................................................................................... 208 7.3.5 Non-Volatile Memory ................................................................................................... 208 7.3.6 Power Control Using HIB ............................................................................................. 209 7.3.7 Power Control Using VDD3ON Mode ........................................................................... 209 7.3.8 Initiating Hibernate ...................................................................................................... 209 7.3.9 Interrupts and Status ................................................................................................... 209 7.4 Initialization and Configuration ..................................................................................... 210 7.4.1 Initialization ................................................................................................................. 210 7.4.2 RTC Match Functionality (No Hibernation) .................................................................... 211 7.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 211 7.4.4 External Wake-Up from Hibernation .............................................................................. 211 7.4.5 RTC or External Wake-Up from Hibernation .................................................................. 212 7.4.6 Register Reset ............................................................................................................ 212 7.5 Register Map .............................................................................................................. 212 7.6 Register Descriptions .................................................................................................. 213 8 Internal Memory ................................................................................................... 230 8.1 Block Diagram ............................................................................................................ 230 8.2 Functional Description ................................................................................................. 230 8.2.1 SRAM ........................................................................................................................ 231 8.2.2 ROM .......................................................................................................................... 231 8.2.3 Flash Memory ............................................................................................................. 233 8.3 Flash Memory Initialization and Configuration ............................................................... 234 8.3.1 Flash Memory Programming ........................................................................................ 234 8.3.2 32-Word Flash Memory Write Buffer ............................................................................. 236 8.3.3 Nonvolatile Register Programming ............................................................................... 236 8.4 Register Map .............................................................................................................. 237 8.5 Flash Memory Register Descriptions (Flash Control Offset) ............................................ 238 June 14, 2010 4 Texas Instruments-Advance Information Table of Contents |
同様の部品番号 - LM3S9790-EQR80-C1 |
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同様の説明 - LM3S9790-EQR80-C1 |
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