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KM416V4104CS-45 データシート(PDF) 8 Page - Samsung semiconductor |
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KM416V4104CS-45 データシート(HTML) 8 Page - Samsung semiconductor |
8 / 36 page KM416V4004C,KM416V4104C CMOS DRAM NOTES An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs. Measured with a load equivalent to 1 TTL load and 100pF. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. Assumes that tRCD ≥tRCD(max). This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric charac- teristics only. If tWCS ≥tWCS(min), the cycles is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD ≥tCWD(min), tRWD≥tRWD(min) and tAWD≥tAWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. Either tRCH or tRRH must be satisfied for a read cycle. This parameters are referenced to the CAS leading edge in early write cycles and to the W falling edge in OE controlled write cycle and read-modify-write cycles. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. These specifiecations are applied in the test mode. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. tASC, tCAH are referenced to the earlier CAS falling edge. tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle. tCWD is referenced to the later CAS falling edge at word read-modify-write cycle. KM416V40(1)04C Truth Table RAS LCAS UCAS W OE DQ0 - DQ7 DQ8-DQ15 STATE H X X X X Hi-Z Hi-Z Standby L H H X X Hi-Z Hi-Z Refresh L L H H L DQ-OUT Hi-Z Byte Read L H L H L Hi-Z DQ-OUT Byte Read L L L H L DQ-OUT DQ-OUT Word Read L L H L H DQ-IN - Byte Write L H L L H - DQ-IN Byte Write L L L L H DQ-IN DQ-IN Word Write L L L H H Hi-Z Hi-Z - 7. 6. 5. 10. 9. 8. 13. 12. 11. 15. 14. 3. 2. 1. 4. |
同様の部品番号 - KM416V4104CS-45 |
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同様の説明 - KM416V4104CS-45 |
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