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KM48V8104C データシート(PDF) 5 Page - Samsung semiconductor |
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KM48V8104C データシート(HTML) 5 Page - Samsung semiconductor |
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5 / 21 page  KM48V8004C,KM48V8104C CMOS DRAM CAPACITANCE (TA=25 °C, VCC=3.3V, f=1MHz) Parameter Symbol Min Max Units Input capacitance [A0 ~ A12] CIN1 - 5 pF Input capacitance [RAS, CAS, W, OE] CIN2 - 7 pF Output capacitance [DQ0 - DQ7] CDQ - 7 pF AC CHARACTERISTICS (0 °C≤TA≤70°C, See note 2) Test condition : VCC=3.3V ±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V Parameter Symbol -45 -5 -6 Units Note Min Max Min Max Min Max Random read or write cycle time tRC 74 84 104 ns Read-modify-write cycle time tRWC 101 113 138 ns Access time from RAS tRAC 45 50 60 ns 3,4,10 Access time from CAS tCAC 12 13 15 ns 3,4,5 Access time from column address tAA 23 25 30 ns 3,10 CAS to output in Low-Z tCLZ 3 3 3 ns 3 Output buffer turn-off delay from CAS tCEZ 3 13 3 13 3 13 ns 6,13 OE to output in Low-Z tOLZ 3 3 3 ns 3 Transition time (rise and fall) tT 1 50 1 50 1 50 ns 2 RAS precharge time tRP 25 30 40 ns RAS pulse width tRAS 45 10K 50 10K 60 10K ns RAS hold time tRSH 8 8 10 ns CAS hold time tCSH 35 38 40 ns CAS pulse width tCAS 7 5K 8 10K 10 10K ns 14 RAS to CAS delay time tRCD 11 33 11 37 14 45 ns 4 RAS to column address delay time tRAD 9 22 9 25 12 30 ns 10 CAS to RAS precharge time tCRP 5 5 5 ns Row address set-up time tASR 0 0 0 ns Row address hold time tRAH 7 7 10 ns Column address set-up time tASC 0 0 0 ns Column address hold time tCAH 7 7 10 ns Column address to RAS lead time tRAL 23 25 30 ns Read command set-up time tRCS 0 0 0 ns Read command hold time referenced to CAS tRCH 0 0 0 ns 8 Read command hold time referenced to RAS tRRH 0 0 0 ns 8 Write command hold time tWCH 7 7 10 ns Write command pulse width tWP 6 7 10 ns Write command to RAS lead time tRWL 8 8 10 ns Write command to CAS lead time tCWL 7 7 10 ns Data set-up time tDS 0 0 0 ns 9 |
同様の部品番号 - KM48V8104C |
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同様の説明 - KM48V8104C |
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