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KM681002CLT-20 データシート(PDF) 4 Page - Samsung semiconductor |
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KM681002CLT-20 データシート(HTML) 4 Page - Samsung semiconductor |
4 / 9 page KM681002C/CL, KM681002CI/CLI CMOS SRAM PRELIMINARY Revision 2.0 - 4 - March 2000 PRELIMINARY TEST CONDITIONS* * The above test conditions are also applied at industrial temperature range. Parameter Value Input Pulse Levels 0V to 3V Input Rise and Fall Times 3ns Input and Output timing Reference Levels 1.5V Output Loads See below AC CHARACTERISTICS(TA=0 to 70 °C, VCC=5.0V±10%, unless otherwise noted.) READ CYCLE* * The above parameters are also guaranteed at industrial temperature range. Parameter Symbol KM681002C-10 KM681002C-12 KM681002C-15 KM681002C-20 Unit Min Max Min Max Min Max Min Max Read Cycle Time tRC 10 - 12 - 15 - 20 - ns Address Access Time tAA - 10 - 12 - 15 - 20 ns Chip Select to Output tCO - 10 - 12 - 15 - 20 ns Output Enable to Valid Output tOE - 5 - 6 - 7 - 9 ns Chip Enable to Low-Z Output tLZ 3 - 3 - 3 - 3 - ns Output Enable to Low-Z Output tOLZ 0 - 0 - 0 - 0 - ns Chip Disable to High-Z Output tHZ 0 5 0 6 0 7 0 9 ns Output Disable to High-Z Output tOHZ 0 5 0 6 0 7 0 9 ns Output Hold from Address tOH 3 - 3 - 3 - 3 - ns Chip Selection to Power Up Time tPU 0 - 0 - 0 - 0 - ns Chip Selection to Power Down- tPD - 10 - 12 - 15 - 20 ns Output Loads(B) DOUT 5pF* 480 Ω 255 Ω for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +5.0V * Including Scope and Jig Capacitance Output Loads(A) DOUT RL = 50 Ω ZO = 50 Ω VL = 1.5V 30pF* * Capacitive Load consists of all components of the test environment. |
同様の部品番号 - KM681002CLT-20 |
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同様の説明 - KM681002CLT-20 |
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