ADuM3160BRWZ-RL datasheet(3/16 Pages) AD

部品番号	ADuM3160BRWZ-RL

部品情報	Full/Low Speed 2.5 kV USB Digital Isolator

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ADuM3160

Rev. A | Page 3 of 16

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

4.5 V ≤ VBUS1 ≤ 5.5 V, 4.5 V ≤ VBUS2 ≤ 5.5 V; 3.1 V ≤ VDD1 ≤ 3.6 V, 3.1 V ≤ VDD2 ≤ 3.6 V. All minimum/maximum specifications apply over

the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. All

voltages are relative to their respective ground.

Table 1.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions1

DC SPECIFICATIONS

Total Supply Current2

1.5 Mbps

VDD1 or VBUS1 Supply Current

IDD1 (L)

5

7

mA

750 kHz logic signal rate, CL = 450 pF

VDD2 or VBUS2 Supply Current

IDD2 (L)

5

7

mA

750 kHz logic signal rate, CL = 450 pF

12 Mbps

VDD1 or VBUS1 Supply Current

IDD1 (F)

6

8

mA

6 MHz logic signal rate, CL = 50 pF

VDD2 or VBUS2 Supply Current

IDD2 (F)

6

8

mA

6 MHz logic signal rate, CL = 50 pF

Idle Current

VDD1 or VBUS1 Idle Current

IDD1 (I)

1.7

2.3

mA

Input Currents

IDD−, IDD+,

IUD+, IUD−,

ISPD, IPIN,

ISPU, IPDEN

−1

+0.1

+1

µA

0 V ≤ VDD−, VDD+, VUD+,VUD−, VSPD, VPIN,

VSPU, VPDEN ≤ 3.0

Single-Ended Logic High Input Threshold

VIH

2.0

V

Single-Ended Logic Low Input Threshold

VIL

0.8

V

Single-Ended Input Hysteresis

VHST

0.4

V

Differential Input Sensitivity

VDI

0.2

V

|VXD+ − VXD−|

Logic High Output Voltages

VOH

2.8

3.6

V

RL = 15 kΩ, VL = 0 V

Logic Low Output Voltages

VOL

0

0.3

V

RL = 1.5 kΩ, VL = 3.6 V

VDD1 and VDD2 Supply Under Voltage Lockout

VUVLO

2.4

3.1

V

VBUS1 Supply Under Voltage Lockout

VUVLOB1

3.5

4.35

V

VBUS2 Supply Under Voltage Lockout

VUVLOB2

3.5

4.4

Transceiver Capacitance

CIN

10

pF

UD+, UD−, DD+, DD− to ground

Capacitance Matching

10

%

Full Speed Driver Impedance

ZOUTH

4

20

Ω

Impedance Matching

10

%

SWITCHING SPECIFICATIONS, I/O PINS, LOW SPEED

Low Speed Data Rate

1.5

Mbps

CL = 50 pF

Propagation Delay3

tPHL, tPLH

325

ns

CL = 50 pF, SPD = SPU = low VDD1,

VDD2 = 3.3 V

Side 1 Output Rise/Fall Time (10% to 90%) Low

Speed

tRF, tFF

75

300

ns

CL = 450 pF, SPD = SPU = low VDD1,

VDD2 = 3.3 V

Low Speed Differential Jitter, Next Transition

|tLJN|

45

ns

CL = 50 pF

Low Speed Differential Jitter, Paired Transition

|tLJP|

15

ns

CL = 50 pF

SWITCHING SPECIFICATIONS, I/O PINS, FULL SPEED

Maximum Data Rate

12

Mbps

CL = 50 pF

Propagation Delay3

tPHL, tPLH

20

60

70

ns

CL = 50 pF

Output Rise/Fall Time (10% to 90%) Full Speed

tR, tFL

4

20

ns

CL = 50 pF, SPD = SPU = high

Full Speed Differential Jitter, Next Transition

|tHJN|

3

ns

CL = 50 pF

Full Speed Differential Jitter, Paired Transition

|tHJP|

1

ns

CL = 50 pF

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